**AppEx is Hiring!**
AppEx is seeking talented individuals to join our team in the following positions:
### **1. Design Verification (DV) Engineer**
- **Experience:** 0-3 years
- **Key Skills:** Verilog, SystemVerilog (SV), Universal Verification Methodology (UVM)
### **2. Design for Test (DFT) Engineer**
- **Experience:** 0-3 years
- **Key Skills:** Scan Insertion, Automatic Test Pattern Generation (ATPG), Boundary Scan, JTAG
### **Qualification:**
- A Bachelor's degree in Electronics and Communication Engineering (ECE) or Electrical and Electronics Engineering (EEE)
If you meet the qualifications and are interested in a dynamic career opportunity, send your resume to **careers@appexsemi.com**.
Join AppEx and be a part of our innovative team!
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